There are several semiconductor memory types available for use in constructing memory components for incorporation in computers and other electronic devices. In addition, there are numerous semiconductor fabrication processes available for forming memory components operating in accordance with the several semiconductor memory types. Further, almost continual progress is being made in process and fabrication techniques, resulting in improvements to component speed and stability of operation and reductions in component size and power consumption. In such a situation it is therefore a continuing challenge to adapt emerging process, fabrication and device improvements to semiconductor memories in such a way that the maximum benefit is derived from the improvements.
For example, regarding semiconductor memory types two are most common—dynamic random access memories (hereinafter “DRAMs”) and static random access memories (hereinafter “SRAMs”). A DRAM memory is comprised of DRAM cells which essentially are capacitors for storing charge; the states of the capacitors constitute the memory states of the DRAM cell. DRAMs have relatively high memory densities in comparison to other memory technologies, for example SRAM memories, but this comes at a cost. For various reasons well-known to those skilled in the art, capacitors comprising the memory cells in DRAM devices cannot maintain their charge states in perpetuity and therefore have to be occasionally refreshed in order not to lose their memory state.
In contrast to DRAMs, SRAMs store information in bistable semiconductor circuits. More devices need to be fabricated in order to construct an SRAM memory cell in comparison to a DRAM memory cell, resulting in DRAMs generally achieving better memory density. On the other hand, SRAMs need not be refreshed in the manner of capacitive DRAMs. In addition, SRAMs generally have shorter read/write cycle times. Thus, SRAMs often are used in microprocessors in so-called “cache memory.”
FIG. 1 shows a cross section of a prior art SRAM through a pair of NFET transistors 142, 144. The NFETs 142, 144 are formed in a thin silicon surface layer 130 that is isolated from an underlying silicon substrate 110 by a buried oxide (BOX) layer 120. In a typically complex series of mask steps, silicon-on-insulator (“SOI”) regions are formed in the silicon surface layer 130 by etching shallow trenches through the surface layer 130 and filling the shallow trenches with oxide to isolate regions from one another. This type of isolation is normally referred to as shallow trench isolation (“STI”). STI is used to isolate circuits formed in the regions from each other and, also, isolate the FETs forming the circuits from each other.
After forming a gate oxide layer on the surface of the silicon regions, gates 116 are patterned and formed at the location of devices 142, 144. Source/drain regions 132 are defined using a standard implant and diffusion step, after forming lightly doped diffusion regions 134 at the gate boundaries, if desired. Device channels 136 are completely isolated from other channels by source/drain diffusions 132 at either end, BOX layer 120 below, gate oxide above and STI (not shown) along the sides of the channel. Further, “halo” regions 133 have been formed between the source/drain regions 132 and channel 136 through a separate diffusion step of the same dopant type used to form the body regions but at a higher concentration.
Ideally, the thin silicon surface layer 130 is no thicker than what is necessary to form a channel 136 between a pair of source/drain diffusions 132. However, in practice, the silicon surface layer can be thicker than the depth of the FET's channel inversion layer. So, when the channel inversion layer forms, i.e., when the FET is turned on, an uninverted layer can remain beneath the channel inversion layer. This uninverted layer remains isolated, resistively, from adjacent regions and any charge that is introduced into the uninverted channel region remains trapped there until it leaks out through junction leakage or is otherwise coupled out. This trapped charge can produce unwanted device channel bias resulting in what is referred to as body effects that are localized to an individual device.
So, these prior art SOI FETs 142, 144 have isolated floating channels (body regions)136 that are not biased by any bias voltage. Thus, the channel bias of any device is dependent upon its current operating state and the device's history, i.e., any remaining charge that has been previously introduced through capacitive coupling or bipolar injection. For typical individual logic circuits such as, decoders, clock buffers, input or output drivers and array output drivers, variations in device characteristics resulting from floating device channels are predicted in device models and are accounted for in chip timing.
Localized body effects present significant problems for CMOS SOI SRAM arrays. This floating body effect allows the body potential and threshold voltage to vary from device to device within a single cell, introducing a use-dependent bias. There are several contributors to this variation or mismatch and body potential is a significant contributor. If the mismatch between devices is sufficiently large the cell will be disturbed during a read or a write operation and even in an idle state. Then data may be lost.
It is known that coupling the bodies of the devices reduces the body potential and threshold mismatch of the devices and so enhances the stability of SRAM cells. Known methods of doing this are to use so-called body-contacted SOI MOSFET transistors. When applied to CMOS SRAM cells, these methods significantly increase cell area and process complexity. The increase in area can be as much as two to three times for each transistor with a small dimension as used in SRAM cells and sums to form at least a two-times-larger SRAM cell. Another drawback is that the parasitic capacitance associated with the polysilicon gate and diffusions of the body-contacted transistor will degrade the SRAM array performance.
Problems have been encountered in other areas as well. Advances have been made in fundamental substrate fabrication techniques which now permit portions of a substrate to be fabricated in silicon with different crystal orientations. It has long been known that PFETs experience improved performance when fabricated in (110) crystal orientation silicon due to the increased mobility of the majority carrier (holes) in (110) crystal orientation silicon. It has only become possible recently to form (110) crystal orientation silicon regions no larger than the PFET devices themselves so that such regions can be incorporated in an otherwise (100) crystal orientation substrate without sacrificing device density. Although advantageous, the hybrid substrate technology must be used judiciously so that the potential improvements in device performance achievable with such technology are not blunted through sub-optimal decisions concerning other design issues, for example, overcoming the floating body effect.
Those skilled in the art thus desire CMOS SRAM cell architectures that overcome the problems associated with the floating body effect without sacrificing the gains made by fabricating the device in SOI, for example, improved read/write speeds and lower power consumption. In particular, such an improved CMOS SRAM cell architecture would have improved stability, and experience far fewer anomalies during read/write operations.
In addition those skilled in the art desire improved SRAM cell layouts that derive increased benefit from linked body technology; in particular, those skilled in the art desire SRAM cell layouts that reduce the resistance encountered in devices having linked bodies.
Further, those skilled in the art also desire the judicious use of state of the art device structures to improve the performance of the logic and memory portions of SRAM memories or microprocessors. In particular, those skilled in the art desire the application of state of the art device structures to improve the speed of logic operations in the logic portion of an SRAM memory or microprocessor and the stability of the memory portion of the SRAM memory or microprocessor.